Welcome to the:
3D Interconnect Wiki
3D integration holds tremendous promise for future integrated circuits. The clear advantages of 3D integration include higher performance, lower power and increased functionality in a smaller form factor. This potential is drawing considerable attention from a wide variety of companies across the semiconductor and MEMS industries.
Through-silicon vias (TSVs) are already in production for CMOS image sensors. High-volume manufacturing for Wide I/O Dynamic Random Access Memory (DRAM) utilizing TSV technology is expected as early as 2013.
The purpose of this wiki is to provide an open forum to discuss the issues which must be resolved before high-volume implementation of 3D integrated circuits becomes a reality.
We welcome your comments and inputs on these topics related to 3D integration as well as any suggestions for directions for new discussions on this Wiki.
3D integration holds tremendous promise for future chips. The clear advantages of 3D integration include higher performance, lower power and increased functionality in a smaller form factor. This potential is drawing considerable attention from a wide variety of companies across the semiconductor and MEMS industries. Despite its high potential, a lack of uniform standards and the limited maturity of key technologies, including processes, design tools, and fabrication equipment have slowed the migration of 3D technologies into mainstream production.
The purpose of this wiki is to provide an open forum to discuss the issues which must be resolved before high-volume implementation of 3D integrated circuits becomes a reality.
These technical challenges are in areas as diverse as chip stacking (heterogeneous, memory stacking, logic on logic), production of through-silicon vias (TSV), interposers using TSV, and basic metrology.
Recently Added
- Guide for Incoming/Outgoing Quality Control and Testing Flow for 3DS-IC Products (D5485)
- Guide for CMP and Micro-bump Processes for Frontside TSV Integration (D5474)
- Guide for Alignment Mark for 3DS-IC Process (D5473)
- Test Method for Measuring Warp, Bow and TTV on Silicon and Glass Wafers Mounted on Wire Grids by Automated Non-Contact Scanning using Laser Scanning Interferometry (D5506)
- Terminology for Measured Geometrical Parameters of Through-Glass Vias (TGVs) in 3DS-IC Structures (D5447)
- Specification for Glass Wafers for Use in Bonded Wafer Stacks (3D2-0113) PUBLISHED STANDARD
- Middle End Process Task Force
- Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks (D5409)
- Wide IO DRAM Memory Specification – Low Power DRAM: Gen 2
- 3DS IC Testing Task Force
Recently Modified
- SEMI Standard Activities
- Specification for Glass Wafers for Use in Bonded Wafer Stacks (3D2-0113) PUBLISHED STANDARD
- Test Method for Wafer Bond Strength Measurements Using Micro-Chevron Test Structures (MS5-1211) PUBLISHED STANDARD
- Guide for CMP and Micro-bump Processes for Frontside TSV Integration (D5474)
- Guide for Multi-Wafer Transport and Storage Containers for Thin Wafers (D5175)
- Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures (D5410)
- Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks (D5409)
- Guide for Describing Materials Properties for a 300 mm 3DS-IC Wafer Stack (D5173D)
- 3D Standards Dashboard
- Wide IO DRAM Memory Specification – Low Power DRAM. PUBLISHED STANDARD: JESD229
