JEDEC Standards Activities

Introduction

To meet industry demands for increased levels of integration as well as improved performance, bandwidth, latency, power, weight and form factor, microelectronics manufacturers are implementing three dimensional chip stacking (3DS-IC) utilizing Through Silicon Via (TSV) chip to chip interconnects. Several JEDEC committees and task groups covering a broad range of technologies are presently working on 3D-IC standards.

List of Standard Activities/Listed by Committee

    JC-11 Mechanical (Package Outlines) Standardization

• Wide IO Mobile Memory Mechanical Outlines (JC-11)

    JC-14 Quality and Reliability of Solid State Products

• 3D-ICs Packaged and Unpackaged Evaluations and Qualifications (JC-14)
• 3DS-ICs Reliability Test Methods (JC-14)
• 3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): Identifying, Evaluating and Understanding Reliability Interactions (JC-14) PUBLISHED STANDARD: JEP158

    JC-40 Digital Logic

• 3D Stack Buffer/Register Support (JC-40)

    JC-42 Solid State Memories

• General Memories and TSVs (JC-42)
• 3D Memory Stack for DDR3 and DDR4 using TSV (JC-42)
• Wide IO DRAM Memory Specification – Low Power DRAM. PUBLISHED STANDARD: JESD229
• Wide IO DRAM Memory Specification – Low Power DRAM: Gen 2

    JC-63 Multiple Chip Packages

• 3D Stacked Mixed Technology (JC-63)